1. Field of the Invention
The present invention relates to a data processor which operates by a pipeline processing system, and specifically relates to a data processor which processes an instruction wherein a source operand is an immediate value, and a destination operand is specified by a register direct addressing mode.
2. Description of Related Art
FIG. 1 is a block diagram showing a configuration of a pipeline processing function of a conventional data processor.
The conventional data processor is constituted with an instruction fetching stage 391, an instruction decoding stage 392, an operand address calculation stage 393, an operand fetch stage 394 and an instruction execution stage 395. Then, an instruction is decomposed into a plurality of unit codes (step codes) for pipeline processing in the decoding stage to be pipeline-processed. Detail of such a data processor has been disclosed in Japanese Patent Application Laid-Open No. 63-89932 (1988).
In the conventional data processor as described above, elements constituting a pipeline are divided into a portion which executes pre-processing of the instruction fetch stage 391, the instruction decoding stage 392, the operand address calculation stage 393, the operand fetch stage 394 and the like and a portion which executes the instruction such as the instruction execution stage 395. The portion of preprocessing executes only pre-processing relating to an operand specified in the instruction. Then, the instruction is executed by the execution stage 395 using the operand prepared by the pre-processing.
However, in such a data processor, as to instructions such as an transfer instruction between a memory and a memory or between a memory and a register which transfer data from a source operand to a destination operand, a unit processing code relating to the source operand and a unit processing code relating to the destination operand are produced on the pipeline. However, in an instruction wherein the source operand is an immediate value and the destination operand is specified by the register direct addressing mode, the unit processing code of destination is not required. Accordingly, in processing an instruction of the register direct addressing mode, wasteful processing of the unit processing code is executed, and the efficiency of the whole of the processor is reduced.
The present invention has been achieved to solve such a problem, and purposes to provide a data processor which can efficiently process an instruction wherein the source operand is an immediate value and the destination operand is specified in the register direct addressing mode on the pipeline.